Systematic defect risk assessment based on silicon digital twins

As semiconductor design scales down and grows in complexity, manufacturing processes face tighter tolerances and increased risk of systematic defects. Identifying an optimal process window that is robust against such defects is traditionally achieved through design-of-experiments (DOE) on actual wafers, which is both time- and cost-intensive. Yield-based analysis provides additional insights but requires fab-out and is limited by the scarcity of defective cases and the sparsity of metrology data, making accurate defect characterization difficult. This paper introduces a virtual silicon process modeling framework based on a 3D TCAD emulator that constructs a silicon digital twin (Si-DT) by simulating fabrication steps directly on a GDS layout. Virtual DOE with Monte Carlo simulations enables the rapid generation of thousands of 3D structures, where process-induced variations and systematic defect margins can be measured at nanometer precision. Statistical modeling is then applied to derive defect indices from virtual silicon metrology data, providing a predictive and interpretable approach to process monitoring and optimization.