Authors
Liñán-Cembrano, G.Domínguez-Castro, R.Espejo-Meana, S.Rodríguez-Vázquez, Ángel
Topics
History of Medicine StudiesHistorical Astronomy and Related StudiesOphthalmology and Visual Health ResearchI-345Abstract** --- This paper presents a new genera tion 128x128 Focal Plane Analog Programmable Array Processor (FPAPAP), from a system level perspective. The design has recently sent to fabri cation in a 0.35µm standard digital 1P-5M CMOS Technology. The chip has been designed to achieve the high-speed and moderate-accuracy constraints of most real time image processing applications. It has been designed to be easily embedded in conventional digital hosting systems: external data interchange and control are com pletely digital. The chip contains close to four mil lions transistors, 80% of them working in analog mode, and exhibits a relatively low power con sumption (<4W, i.e. less than 1mW per transis tor). Experimental results are expected for the date of paper presentation.1 Introduction. Conventional vision systems use a CCD camera for parallel acquisition of the input image, and serial trans mission of a digitized version of the input data to a sep arate computer. This approach results in huge data rates which conventional computers can not analyze in real time. Conventional computers and DSPs are able to manage such data rates for simple tasks like auto-focus, image stabilization, control of the luminance/chromi nance, etc. However, the real-time execution of most spatial-temporal operations typical of front-end image processing tasks requires much more sophisticated digi tal processors. Consequently, conventional vision machines with real-time capabilities are bulky, expen sive and extremely power-hungry. The contrast between the performance of artificial and “natural” vision sys tems is due, among other things, to the inherent paral lelism of the latter. Inspired by the efficiency of natural vision systems, universities and companies have focused their efforts on the development of new generations of devices, aiming to overcome the drawbacks of traditional ones by means of distributed parallel processing and concurrent signal acquisition and storage. One possible strategy is flip-chip bonding of separate sensing and processing devices. Another alternative is to “fuse” the sensory and the processing circuitry on the same semiconductor substrate. “Silicon retinas”, “smart-pixel chips” and “focal-plane array-processors” are members of this lat ter class of vision chips [1][2]. Their development is expected to have a significant impact in quite diverse scenarios. However, industrial applications demand flexible and versatile chips, with programmable func tions, distributed storage, and standard interfacing to conventional equipment. ACE16k, with its increased complexity and fully digital interface, is conceived to be one step closer to industrial applications than previ ous FPAPAPs prototypes.
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PublishedJan 1, 2001
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