Publication

Embedded deterministic test for low cost manufacturing test

Jun 25, 2003 · 11 authors · 3 topics

Abstract

This paper introduces embedded deterministic test (EDT) technology, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The EDT architecture, the compression algorithm, design flow, experimental results, and silicon implementation are presented.

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Authors

8 of 11
Janusz RajskiJerzy TyszerMark KassabNilanjan MukherjeeR. ThompsonKun-Han Hans TsaiAndre HertwigNagesh Tamarapalli

Topics

VLSI and Analog Circuit TestingIntegrated Circuits and Semiconductor Failure AnalysisEngineering and Test Systems

About

PublishedJun 25, 2003
Citations404
References21

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