Metallization for integrated circuits using a lift-off technique

Abstract

A special lift-off technique for realizing small metal interconnection geometries for integrated circuits is described. 0.6-/spl mu/m gaps between metal conductors can be obtained even at 0.8-/spl mu/m metal layer thickness. The slopes of the conductors are tapered. Etching problems inherent in alloy films or sandwiched layers such as Al/Si or Al/Cu/Si are avoided by the technique proposed. SEM micrographs of Al/Si conductor patterns are presented.

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